1. Field of the Invention
The present invention generally relates to a reticle inspecting technique and particularly to a reticle inspecting method and apparatus for detecting a defect on a reticle by comparing a reference image with image data that is obtained by scanning a pattern drawn on the reticle.
2. Description of the Related Art
In recent years, the packing density of electronic devices has become higher to achieve higher speed and larger capacity of a system LSI (large scale integration) and the like. Accordingly, the structure of a reticle used as an original to manufacture LSIs has become ultrafine, and thus a highly sensitive reticle inspecting apparatus is required. If a reticle has any minute defect thereon, the performance of an entire semiconductor LSI degrades. Therefore, accurately inspecting the reticle (original) is very important.
The inspecting method of the present mainstream is a data comparing inspection called “Die-to-Data Base”. In “Die-to-Data Base”, a defect of a circuit pattern formed on a reticle is detected by comparing actual measurement data (actual image) obtained by laser-scanning the same circuit pattern that is repeatedly formed on the retile with inspection data (reference image).
FIG. 1 is a flowchart showing a known reticle inspecting method. In this method, design data is created by a CAD (computer-aided design) or the like in a work station (S101), and the design data is converted to exposure data of a form suitable for a drawing device (S102). Also, the design data is converted to generate inspection data, which is a reference image as similar as possible to the pattern formed on an actual reticle (S103). Then, the pattern is drawn on the reticle based on the exposure data (S104). At this time, the registration accuracy of the pattern transferred onto a wafer, that is, the position accuracy of the pattern drawn on the reticle is measured so as to suppress the amount of distortion of the pattern on the wafer to a predetermined value or smaller and to ensure that the pattern is reliably stacked without problem when the pattern is transferred onto the wafer by using the reticle (S105).
In a process of inspecting a defect of the created reticle, the reticle is set on an inspecting apparatus (S106), alignment between the reticle pattern and the inspection data is performed (S107), and a correction amount is calculated (S108). Based on the calculated correction amount, the inspection data is uniformly corrected (S109).
Then, inspection starts and the corrected inspection data is compared to the reticle pattern (S110). After the inspection (S111), if a defect has been detected, defect information is stored (S113) and the residual defect on the reticle is corrected based on the defect information (S114). If no defect has been detected, the process proceeds to the next process (S115).
Assume that, as shown in FIG. 2A, a reticle 100 is set on the inspecting apparatus while being misaligned relative to a horizontal axis H in the alignment step S107. In this example, as shown in FIG. 2B, which is an enlarged view of the alignment pattern, the alignment pattern 110 on the reticle 100 is misaligned with the inspection data by an angle θ. In such a case, a stage is rotated so that the reticle is brought into alignment with the inspection data. The misalignment of the angle θ is used as correcting information to correct the inspection data.
FIGS. 3A to 3C show an example of a known uniform correction. As shown in FIGS. 3A to 3C, shrinkage ratio information of the reticle pattern is obtained at alignment. For example, FIG. 3A shows the alignment pattern and inspection data before correction. As shown in FIG. 3A, the alignment pattern drawn on the reticle is internally shrunk compared to the design data (that is, the inspection data). FIG. 3B shows an entire pattern including the above-described alignment pattern and a pattern corresponding to the circuit pattern of a device (hereinafter referred to simply as “circuit pattern”). In this case, the entire circuit pattern drawn on the reticle is internally shrunk. Then, as shown in FIG. 3C, the entire inspection data is uniformly corrected by internally shrinking it based on the shrinkage ratio information (for the entire pattern before correction shown in FIG. 3A).
As described above, in the known correcting method, a plurality of chip areas defined on the data are uniformly corrected by using the correction information (shrinkage ratio and rotation component) obtained at the alignment before inspection. In other words, the inspection data is linearly corrected by being multiplied by a predetermined correction value (x, y, and θ), and then inspection of the reticle is performed.
However, as shown in FIGS. 4A and 4B, the actual reticle includes a local misalignment and a variation in the shrinkage ratio that cannot be corrected by a uniform correction. FIG. 4A shows an ideal grid representing a chip alignment with no misalignment overlaid with a pattern formed on the actual reticle having a local misalignment amount. As shown in FIG. 4A, the pattern actually formed on the reticle includes a misalignment that can be measured by the nanometer (nm) with respect to the ideal grid (chip alignment). Actually, a nonuniform local misalignment (misalignment in position and variation in shrinkage ratio) occurs not only in each chip but also in each minute area of a matrix of the chip. Due to such a local misalignment, difference in shrinkage ratio still exists between the inspection data and the actual reticle even after the shrinkage correction has been done on the inspection data, as shown in FIG. 4B. FIG. 4B shows a state where uniform correction has been done based on the shrinkage ratio of the actual reticle, with respect to FIG. 4A showing the amount of local misalignment between the ideal grid and the actual reticle. A factor of such a misalignment includes a conventional uniform misalignment and a local misalignment. Therefore, the conventionally used uniform correcting method can cause an alignment error or a false defect. In other words, even if uniform correction is performed, inspection is performed under existence of difference from the actual reticle pattern. Thus, many alignment errors and false defects occur during the inspection. As a result, the inspection is frequently interrupted.
A method for correcting measurement data by considering expansion/shrinkage of a circuit pattern caused by deflection in the vertical direction to the principal surface of a reticle with regard to a variation component on the reticle has been suggested (e.g., see Japanese Unexamined Patent Application Publication No. 5-87544). In this method, a variation in the Z direction (height direction) of a reticle is measured by using an auto-focus function of a lens, the amount of deflection of the reticle is obtained by analysis, and the measurement data is corrected by reflecting the amount of deflection thereto.
Also, a method for preventing detection of a false defect by performing defect inspection while correcting distortion of pitches in the Y direction of a scanner during defect detection has been suggested (e.g., see Japanese Unexamined Patent Application Publication No. 2000-348177). In this method, a correcting pattern as well as a circuit pattern is drawn on a reticle, a correction table is created by measuring variation in advance pitches in the Y direction of a scan mechanism, and then an input image (scanned image) is corrected in the Y direction by referring to the correction table during inspection.
The invention described in Japanese Unexamined Patent Application Publication No. 5-87544 is directed to correcting measurement values of a line width and a distance between lines measured during inspection of a defect. More specifically, the invention described in this patent document is directed to correcting length measurement data of a pattern by measuring a variation in the height direction caused by deflection of a reticle, and does not suggest an effective solution to suppress the occurrence of a false defect caused by a nonuniform local misalignment or variation in the shrinkage ratio.
On the other hand, the invention described in Japanese Unexamined Patent Application Publication No. 2000-348177 is directed to correction about the advance accuracy (aliasing accuracy) of a scanner device, and is particularly directed to correcting a pitch distortion to realize regular pitch at inspection of a defect by measuring in advance variation in advance pitch in the Y direction of the scanner device and creating a correction table.
However, in the future highly-accurate reticle inspection, the target of the inspection is a circuit including an area of high pattern density, such as a logic circuit, and an area of low pattern density, such as an isolated pattern. In that case, correction needs to be performed in a more detailed level than the deflection of a surface of a reticle or variation in advance pitch of the scanner device. That is, required is a reticle inspecting technique of performing inspection on a circuit including a high-density pattern and an isolated pattern with a high defect detecting sensitivity and suppressing an alignment error and a false defect. Incidentally, the “false defect” means a defect that is falsely determined to be a pattern defect in an inspection although a pattern defect, such as break of line, is not actually caused. The false defect is likely to occur when the entire pattern includes a misalignment.
The present invention has been made in view of the above-described problems, and a main object thereof is to provide a reticle inspecting method and a reticle inspecting apparatus capable of detecting a local misalignment on a reticle with high accuracy, efficiently suppressing the occurrence of a false defect, and detecting a defect with high detecting sensitivity.